Placeholder Pass Metadata Reference

Verilog placeholder pass

class pymtl3.passes.backends.verilog.VerilogPlaceholderPass.VerilogPlaceholderPass(debug=False)

__init__(debug=False)

Initialize self. See help(type(self)) for accurate signature.

__call__(m)

Pickle every Placeholder in the component hierarchy rooted at m.

Here are the available input metadata of the Verilog translation-import pass:

class pymtl3.passes.backends.verilog.VerilogPlaceholderPass.VerilogPlaceholderPass(debug=False)

params = <pymtl3.dsl.MetadataKey.MetadataKey object>

A dict that maps the module parameters to their values.

Type: { str : int }; input

Default value: {}

port_map = <pymtl3.dsl.MetadataKey.MetadataKey object>

A dict that maps the PyMTL port name to the external source port name.

Type: { port : str }; input

Default value: {}

separator = <pymtl3.dsl.MetadataKey.MetadataKey object>

Separator string used by name-mangling of interfaces and arrays. For example, with the default value, s.ifc.msg will be mangled to ifc_msg.

Type: str; input

Default value: '_'

src_file = <pymtl3.dsl.MetadataKey.MetadataKey object>

Path to the external source file.

Type: str; input

Default value: <top_module>.v

top_module = <pymtl3.dsl.MetadataKey.MetadataKey object>

Top level module name in the external source file.

Type: str; input

Default value: PyMTL component class name

v_flist = <pymtl3.dsl.MetadataKey.MetadataKey object>

List of Verilog source file paths.

Type: [str]; input

Default value: []

v_include = <pymtl3.dsl.MetadataKey.MetadataKey object>

List of Verilog include directory paths.

Type: [str]; input

Default value: []

v_libs = <pymtl3.dsl.MetadataKey.MetadataKey object>

List of Verilog library file paths. These files will be added to the beginning of the pikcling result.

Type: [str]; input

Default value: []