Import Pass Metadata Reference¶

Verilog import pass¶

class pymtl3.passes.backends.verilog.import_.VerilogVerilatorImportPass.VerilogVerilatorImportPass(debug=False)¶

Import an arbitrary SystemVerilog module as a PyMTL component.

__init__(debug=False)¶: Initialize self. See help(type(self)) for accurate signature.

__call__(top)¶: Import the PyMTL component hierarhcy rooted at top.

Here are the available input and output metadata of the Verilog import pass:

class pymtl3.passes.backends.verilog.import_.VerilogVerilatorImportPass.VerilogVerilatorImportPass(debug=False)

Import an arbitrary SystemVerilog module as a PyMTL component.

c_flags = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Optional flags to be passed to the C compiler.

Type: str; input

Default value: ''

c_include_path = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Optional include paths to be passed to the C compiler.

Type: [str]; input

Default value: []

c_srcs = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Optional source file paths to be passed to the C compiler.

Type: [str]; input

Default value: []

enable = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable import on a component.

Type: bool; input

Default value: False

fast = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Spend more time on compilation for faster simulation performance

Type: bool; input

Default value: False

import_config = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

An instnace of VerilatorImportConfigs containing the parsed options.

Type: VerilatorImportConfigs; output

ld_flags = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Optional flags to be passed to LD.

Type: str; input

Default value: ''

ld_libs = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Optional libraries to be passed to LD (e.g., '-lfoo').

Type: str; input

Default value: ''

verbose = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Print out extra debug information during import.

Type: bool; input

Default value: False

vl_W_fatal = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilator fatal warnings.

Type: bool; input

Default value: True

vl_W_lint = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilator lint warnings.

Type: bool; input

Default value: True

vl_W_style = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilator style warnings.

Type: bool; input

Default value: True

vl_Wno_list = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

A list of suppressed Verilator warnings.

Type: [str]; input

Default value: ['UNSIGNED', 'UNOPTFLAT', 'WIDTH']

vl_coverage = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilator coverage.

Type: bool; input

Default value: False

vl_enable_assert = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilog assert.

Type: bool; input

Default value: False

vl_line_coverage = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilator line coverage.

Type: bool; input

Default value: False

vl_line_trace = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Use Verilog line_trace output as the Python line_trace return value.

Type: bool; input

Default value: False

vl_mk_dir = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Specify the Verilator make directory.

Type: str; input

Default value: obj_<top-component-name>

vl_opt_level = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Verilator optimization level.

Type: int; input

Default value: 3

vl_toggle_coverage = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilator toggle coverage.

Type: bool; input

Default value: False

vl_trace = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Enable Verilator VCD tracing.

Type: bool; input

Default value: False

vl_trace_cycle_time = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Cycle time of PyMTL clk pin in the generated Verilator VCD in unit of vl_trace_timescale.

Type: int; input

Default value: 100

vl_trace_filename = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Filename of Verilator VCD tracing.

Type: str; input

Default value: translated-component-name.verilator1

vl_trace_on_demand = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Set to true to allow for on-demand VCD dumping

Type: bool; input

Default value: False

vl_trace_on_demand_portname = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Top level port name that is used to enable VCD dumping when vl_trace_on_demand is True. Assuming the port is an active-high enable signal.

Type: str; input

Default value: ""

vl_trace_timescale = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Time scale of generated Verilator VCD.

Type: str; input

Default value: '10ps'

vl_unroll_count = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Verilator unroll count.

Type: int; input

Default value: 1000000

vl_unroll_stmts = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Verilator unroll statement count.

Type: int; input

Default value: 1000000

vl_xinit = <pymtl3.dsl.MetadataKey.MetadataKey object>¶

Verilator initialization options.

Possible values: 'ones', 'zeros', 'rand', and non-zero integers; input

Default value: 'zeros'

Yosys import pass¶

class pymtl3.passes.backends.yosys.import_.YosysVerilatorImportPass.YosysVerilatorImportPass(debug=False)¶

__init__(debug=False)¶: Initialize self. See help(type(self)) for accurate signature.

__call__(top)¶: Import the PyMTL component hierarhcy rooted at top.

The available input and output metadata of the Yosys import pass are the same as those of the Verilog import pass.