Translation Pass Metadata Reference

Verilog translation pass

class pymtl3.passes.backends.verilog.translation.VerilogTranslationPass.VerilogTranslationPass(debug=False)

Translate a PyMTL component hierarchy into Verilog.

__init__(debug=False)

Initialize self. See help(type(self)) for accurate signature.

__call__(top)

Translate a PyMTL component hierarhcy rooted at top.

Here are the available input and output metadata of the Verilog translation pass:

class pymtl3.passes.backends.verilog.translation.VerilogTranslationPass.VerilogTranslationPass(debug=False)

Translate a PyMTL component hierarchy into Verilog.

enable = <pymtl3.dsl.MetadataKey.MetadataKey object>

Enable translation on a component.

Type: bool; input

Default value: False

explicit_file_name = <pymtl3.dsl.MetadataKey.MetadataKey object>

Specify the filename of the translated source file.

Type: str; input

Default value: value of explicit_module_name of the top level

explicit_module_name = <pymtl3.dsl.MetadataKey.MetadataKey object>

Specify the translated name of the component.

Type: str; input

Default value: component class name concatenated with parameters

is_same = <pymtl3.dsl.MetadataKey.MetadataKey object>

Whether or not the translated result is the same as the existing output file.

Type: bool; output

no_synthesis = <pymtl3.dsl.MetadataKey.MetadataKey object>

Wrap component translation result within `ifndef SYNTHESIS Enabling this option effectively removes the component from the hierarchy during logic synthesis.

Type: bool; input

Default value: False

no_synthesis_no_clk = <pymtl3.dsl.MetadataKey.MetadataKey object>

In the translated source, wrap the clk port connection of the component within `ifndef SYNTHESIS. This option can only be enabled while no_synthesis is True. Enabling this option effectively removes the clk pin of the component during logic synthesis.

Type: bool; input

Default value: False

no_synthesis_no_reset = <pymtl3.dsl.MetadataKey.MetadataKey object>

In the translated source, wrap the reset port connection of the component within `ifndef SYNTHESIS. This option can only be enabled while no_synthesis is True. Enabling this option effectively removes the reset pin of the component during logic synthesis.

Type: bool; input

Default value: False

translate_config = <pymtl3.dsl.MetadataKey.MetadataKey object>

An instance of TranslationConfigs that contains the parsed options.

Type: TranslationConfigs; output

translated = <pymtl3.dsl.MetadataKey.MetadataKey object>

Whether or not the component has been translated.

Type: bool; output

translated_filename = <pymtl3.dsl.MetadataKey.MetadataKey object>

Filename of the translation result.

Type: str; output

translated_top_module = <pymtl3.dsl.MetadataKey.MetadataKey object>

Top level module name in the translation result.

Type: str; output

translator = <pymtl3.dsl.MetadataKey.MetadataKey object>

A reference of the translator called during translation.

Type: output

Yosys translation pass

class pymtl3.passes.backends.yosys.translation.YosysTranslationPass.YosysTranslationPass(debug=False)

__init__(debug=False)

Initialize self. See help(type(self)) for accurate signature.

__call__(top)

Translate a PyMTL component hierarhcy rooted at top.

The available input and output metadata of the Yosys translation pass are the same as those of the Verilog translation pass.